The Xenos is a custom graphics processing unit (GPU) designed by ATI (now taken over by AMD), used in the Xbox 360 video game console developed and produced for Microsoft. Developed under the codename “C1”, it is in many ways related to the R520 architecture and therefore very similar to an ATI Radeon X1900 series of PC graphics cards as far as features and performance are concerned. However, the Xenos introduced new design ideas that were later adopted in the TeraScale microarchitecture, such as the unified shader architecture. The package contains two separate dies, the GPU and an eDRAM, featuring a total of 337 million transistors.
The chip is based on an ATI Radeon X1800 XL, the shader units are organized in three SIMD groups with 16 processors per group, for a total of 48 processors. Each of these processors is composed of a 5-wide vector unit (total 5 FP32 ALUs) that can serially execute up to two instructions per cycle (a multiply and an addition). Thus each of the 48 processors can perform 10 floating-point ops per cycle. All processors in a SIMD group execute the same instruction, so in total up to three instruction threads can be simultaneously under execution.
500 MHz parent GPU on 90 nm, 65 nm (since 2008) TSMC process or 45nm GlobalFoundries process (since 2010, with CPU on same die) of total 232 million transistors
48 vector units floating-point vector processors for shader execution, divided in three dynamically scheduled SIMD groups of 16 processors each.
Unified shading architecture (each pipeline is capable of running either pixel or vertex shaders)
10 FP ops per vector processor per cycle (5 fused multiply-add)
Maximum vertex count: 1.21 Billion vertices per second (48 shader vector processors × 2 ops per cycle × 500 MHz) / 8 vector ops per vertex) for simple transformed and lit polygons
Maximum polygon count: 406 million polygons per second
XENOS GPU & XENON CPU: 500 million polygons per secound
Maximum shader operations: 48 billion shader operations per second (3 shader pipelines × 16 processors × 2 ALUs × 500 MHz)
MEMEXPORT shader function
16 texture filtering units (TF) and 16 texture addressing units (TA)
16 filtered samples per clock
Maximum pixel fillrate: 4.00 GPixel/s
Maximum texel fillrate: 8 gigatexels per second (16 textures × 500 MHz)
16 unfiltered texture samples per clock
Maximum dot product operations: 24 billion per second
Support for a supers